The following schedule is tentative and subject to change without notice.

Day Topic Reading
9/4 Course overview Chap. 1
9/6 Integers Chap. 2.1-2.3
9/11
9/13 Floating Points Chap. 2.4
9/18
9/20 Machine-level Representation of Programs Chap. 3.1-3.3
9/25 National holiday
9/27
10/2
10/4 Assembly I: Basic Operations Chap. 3.4-3.5
10/9 National holiday
10/11
10/16 Assembly II: Control Flow Chap. 3.6
10/18 Assembly III: Procedures Chap. 3.7-3.10
10/23
10/25
10/30 Y86-64 ISA Chap. 4.1
11/1 Midterm Exam
11/6
11/8 Logic Design Chap. 4.2
11/13 No class
11/15 No class
11/20 Sequential Y86-64 Implementation Chap. 4.3
11/22 Pipelining Chap. 4.4
11/27 Basic Pipelined Y86-64 Implementation Chap. 4.5
11/29 Complete Pipelined Y86-64 Implementation Chap. 4.5
CPU Performance Chap. 5.7
11/29 Supplementary Class I-A (6:30pm ~ 9:30pm, #301-203)
11/30 Supplementary Class I-B (4:00pm ~ 7:00pm, #301-551)
12/4 The Memory Hierarchy Chap. 6.1-6.3
12/6 Cache Memories Chap. 6.4-6.6
Virtual Memory Chap. 9
12/6 Supplementary Class II-A (6:30pm ~ 9:30pm, #301-203)
12/7 Supplementary Class II-B (4:00pm ~ 7:00pm, #301-551)
12/11 Exceptions and Interrupts Chap. 8.1
12/13 Final Exam

Credit: Some of slides for this lecture are based on materials provided by the textbook publisher.