The following schedule is tentative and subject to change without notice.

Day Topic Reading
3/5 Course Overview Chap. 1
3/7 Integers Chap. 2.1-2.3
3/12 Floating Points Chap. 2.4
3/14
3/19 Machine-level Representation of Programs Chap. 3.1-3.3
3/21
3/26 Assembly I: Basic Operations Chap. 3.4-3.5
3/28
4/2 Assembly II: Control Flow Chap. 3.6
4/4
4/9 Assembly III: Procedures Chap. 3.7-3.10
4/11
4/16
4/18 Y86-64 ISA Chap. 4.1
4/23 Logic Design Chap. 4.2
4/25 Sequential Y86-64 Implementation Chap. 4.3
4/30 Midterm Exam
5/2
5/7 Pipelining Chap. 4.4
5/9 Pipelined Y86-64 Implementation Chap. 4.5
5/14
5/16 CPU Performance Chap. 5.7
5/21 Canceled
5/23 Canceled
5/28 The Memory Hierarchy Chap. 6.1-6.3
5/30 Cache Memories Chap. 6.4-6.6
5/31 Supplementary Class I-A (6:30pm ~ 9:00pm @ #301-551)
6/3 Supplementary Class I-B (6:30pm ~ 9:00pm @ #301-551)
6/4 Virtual Memory Chap. 9
6/6 National holiday
6/7 Supplementary Class II-A (6:30pm ~ 9:00pm @ #301-551)
6/10 Supplementary Class II-B (6:30pm ~ 9:00pm @ #301-551)
6/11 Exceptions and Interrupts Chap. 8.1
6/13 Final Exam

Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.