The following schedule is tentative and subject to change without notice.
Day Topic Reading 9/3 Course Overview (Revised on 9/16) Chap. 1 (except 1.6, 1.9) 9/5 9/10 Integers (Revised on 9/16) Chap. 2.4, 3.1-3.4, 3.6 9/12 National Holiday 9/17 9/19 Floating Points Chap. 2.3, 2.9, 3.5, 3.9-3.10 9/20 Supplementary Class (6:30pm ~ 8:30pm) 9/24 RISC-V Architecture I (Revised on 9/25) Chap.
For project submission and automatic grading, we are running a dedicated server at http://sys.snu.ac.kr. If you want to access the sys server outside of the SNU campus, please send a mail to the instructor.
Project #4: A 3-Stage Pipelined RISC-V Simulator The goal of this project is to understand how a pipelined processor works. You need to build a 3-stage pipelined RISC-V simulator called “snurisc3” in Python that supports most of RV32I base instruction set.
When 9:30 - 10:45 (Tuesday / Thursday) Where Lecture room #301-203, Engineering Building I Instructor Jin-Soo Kim Professor, Dept. of Computer Science and Engineering, SNU Language English Course Description This course introduces the main components of a modern computer system including the instruction set, the processor, and the memory hierarchy. We cover techniques such as pipelining, caching, and virtual memory.
