The following schedule is tentative and subject to change without notice.

Day Topic Reading
9/3 Course Overview (Revised on 9/16) Chap. 1 (except 1.6, 1.9)
9/5
9/10 Integers (Revised on 9/16) Chap. 2.4, 3.1-3.4, 3.6
9/12 National Holiday
9/17
9/19 Floating Points Chap. 2.3, 2.9, 3.5, 3.9-3.10
9/20 Supplementary Class (6:30pm ~ 8:30pm)
9/24 RISC-V Architecture I (Revised on 9/25) Chap. 2.1-2.3, 2.6
9/26
10/1 RISC-V Architecture II (Revised on 10/5) Chap. 2.7-2.8, 2.10, 2.13-2.14
10/3 National Holiday
10/4 Supplementary Class (6:30pm ~ 8:30pm @ 301-302)
10/8 Machine-level Representation of Programs Chap. 2.5, 2.12
10/10 CISC vs. RISC Chap. 2.16-2.20
10/15 School Holiday
10/17 Midterm Exam
10/22 Logic Design Chap. 4.2, Appendix A
10/24 Performance Chap. 1.6, 1.9, 2.13
10/29 Sequential Processor Chap. 4.1, 4.3-4.4
10/31 Pipelining Chap. 4.5
11/5
11/7 Pipelined Processor Chap. 4.6-4.9
11/12
11/14 Advanced Processor Architecture Chap. 4.10-4.11, 4.14-4.15
11/15 Supplementary Class (6:30pm ~ 8:30pm @ 301-302)
11/19 Memory Hierarchy Chap. 5.1-5.2
11/21 Cache Chap. 5.3
11/26 Cache Optimization Chap. 5.4
11/28
12/3 Virtual Memory Chap. 5.7-5.8, 5.13, 5.16-5.17
12/5
12/10 Course Wrap-up
12/12 Final Exam

Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.