For project submission and automatic grading, we are running a dedicated server at http://sys.snu.ac.kr. If you want to access the sys server outside of the SNU campus, please send a mail to the TAs at snucsl.ta AT gmail.
The RISC-V Instruction Set Manual Volume I: Unprivileged ISA (version 20191213) Project #4: A 6-stage Pipelined RISC-V Simulator The goal of this project is to understand how a pipelined processor works.
When 11:00 - 12:15 (Monday / Wednesday) Where Online lecture using zoom Instructor Jin-Soo Kim Professor, Dept. of Computer Science and Engineering, SNU Language English Course Description This course introduces the main components of a modern computer system including the instruction set, the processor, and the memory hierarchy. We cover techniques such as pipelining, caching, and virtual memory.
