The following schedule is tentative and subject to change without notice.
| Day | Topic | Reading |
|---|---|---|
| 9/2 | Course Overview (Online) | |
| 9/7 | Introduction to Computer Architecture (Online) | Chap. 1 (except 1.6, 1.9) |
| 9/9 | Integers (Online) | Chap. 2.4, 3.1-3.4, 3.6 |
| 9/10 | Lab. session #1 @ 7:00pm (Online) | |
| 9/14 | ||
| 9/16 | ||
| 9/21 | Floating Points (Online) | Chap. 2.3, 2.9, 3.5, 3.9-3.10 |
| 9/23 | ||
| 9/28 | ||
| 9/28 | Lab. session #2 @ 7:00pm (Online) | |
| 9/30 | National Holiday | |
| 10/5 | RISC-V Architecture I (Online) | Chap. 2.1-2.3, 2.6 |
| 10/7 | ||
| 10/12 | RISC-V Architecture II (Online) | Chap. 2.7-2.8, 2.10, 2.13-2.14 |
| 10/14 | ||
| 10/19 | Midterm Exam (Offline) | |
| 10/21 | ||
| 10/26 | Machine-level Representation of Programs (Online) | Chap. 2.5, 2.12, 2.16-2.20 |
| 10/26 | Lab. session #3 @ 7:00pm (Online) | |
| 10/28 | Sequential Processor (Updated on Nov. 9) (Online) | Chap. 4.1-4.4 |
| 11/2 | ||
| 11/4 | ||
| 11/9 | Pipelining (Online) | Chap. 4.5 |
| 11/11 | Pipeline Hazards (Online) | Chap. 4.6-4.9 |
| 11/16 | ||
| 11/18 | ||
| 11/20 | Invited Talk @ 2:00pm: The Behind Story, Present, and Future of RISC-V from a RISC-V Co-Inventor (Yunsup Lee, SiFive, Inc.) (Online) | |
| 11/23 | Memory Hierarchy (Online) | Chap. 5.1-5.2 |
| 11/25 | Cache (Online) | Chap. 5.3 |
| Lab. session #4 @ 7:00pm (Online) | ||
| 11/26 | Performance (Supplementary Class @ 7:00pm) (Online) | Chap. 1.6, 1.9, 2.13 |
| 11/30 | Cache Optimization (Online) | Chap. 5.4 |
| 12/2 | ||
| 12/4 | Advanced Processor Architecture (Supplementary Class @ 7:00pm)(Online) | Chap. 4.10-4.11, 4.14-4.15 |
| 12/7 | Virtual Memory (Online) | Chap. 5.7-5.8, 5.13, 5.16-5.17 |
| 12/9 | ||
| 12/14 | Final Exam (Offline) |
Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.